CY62167EV30LL-45ZXI
现货，推荐
符合RoHS标准
无铅

CY62167EV30LL-45ZXI

Infineon's Industrial-Qualified 16Mb MoBL™ SRAM: High-Density, Parallel Interface, and Wide Operating Range
数据手册
封装

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CY62167EV30LL-45ZXI
CY62167EV30LL-45ZXI
数据手册


商品详情

  • 密度
    16 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 范围
    2.2 V 至 3.6 V
  • 引线球表面
    Ni/Pd/Au
  • 接口
    Parallel
  • 目前计划的可用性至少到
    2033
  • 系列
    MoBL™ SRAM
  • 组织(X x Y)
    1M x 16
  • 质量等级
    Industrial

推荐的
OPN
CY62167EV30LL-45ZXI
产品状态 active and preferred
英飞凌封装名称
PG-TSOP-48
封装名 TSOP-I-48 (51-85183)
封装尺寸 960
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
预估长期供货截止日期 2033
产品发布日期 03/2022
封装产地
TH
晶圆产地
TW,US

产品状态
Active
英飞凌封装名称
PG-TSOP-48
封装名 TSOP-I-48 (51-85183)
封装尺寸 960
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
预估长期供货截止日期 2033
产品发布日期 03/2022
封装产地
TH
晶圆产地
TW,US
CY62167EV30LL-45ZXI is a 16-Mbit (1M × 16/2M × 8) CMOS asynchronous SRAM with a 45 ns speed grade in a Pb-free 48-pin TSOP I package. It operates from 2.2 V to 3.6 V across –40°C to +85°C, and offers byte control via BLE/BHE plus automatic power-down when deselected. Operating current is 7 mA typ at 1 MHz and 35 mA max at fmax, with standby as low as 1.5 µA typ (12 µA max) for battery-backed designs.

特性

  • 16-Mbit SRAM: 1M×16 or 2M×8
  • 45 ns read/write cycle time
  • OE access time 22 ns max
  • 2.2 V to 3.6 V single-supply
  • Auto power-down on deselect
  • Active current 7 mA typ at 1 MHz
  • Standby current 1.5 µA typ
  • Max standby current 12 µA
  • Data retention at VCC down to 1.5 V
  • Data retention current 10 µA max
  • 10 pF max input/output capacitance
  • Tri-state outputs via OE/CE/BHE/BLE

产品优势

  • Fits x16 or x8 bus architectures
  • 45 ns timing supports fast CPUs
  • 22 ns OE cuts read access delay
  • 2.2-3.6 V works with 3 V rails
  • Auto power-down saves energy
  • 7 mA typ reduces active power
  • 1.5 µA standby extends battery life
  • 12 µA max eases power budgeting
  • 1.5 V retention keeps data in sleep
  • 10 µA max enables long backup
  • 10 pF loads simplify signal timing
  • Tri-state I/O eases bus sharing
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