CY7C1512KV18-250BZC
现货，推荐

CY7C1512KV18-250BZC

数据手册
封装

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CY7C1512KV18-250BZC
CY7C1512KV18-250BZC
数据手册


商品详情

  • Frequency
    250 MHz
  • 密度
    72 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    0 °C 至 70 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Pb
  • 接口
    Parallel
  • 系列
    QDR-II
  • 组织(X x Y)
    4M x 18
  • 质量等级
    Commercial

推荐的
OPN
CY7C1512KV18-250BZC
产品状态 active and preferred
英飞凌封装名称
P-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 680
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 No
无卤素 Yes
符合RoHS标准 No
封装产地
TW
晶圆产地
TW

产品状态
Active
英飞凌封装名称
P-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 680
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TW
晶圆产地
TW
CY7C1512KV18-250BZC is a 72-Mbit QDR II synchronous pipelined SRAM in a 4M × 18 organization with separate read and write ports to eliminate bus turnarounds. It supports a two-word burst and DDR data transfers, operating up to 250 MHz. The device uses 1.7 V to 1.9 V VDD and 1.4 V to VDD VDDQ, and is offered in a 165-ball FBGA package for high-bandwidth networking, communications, and compute systems.

特性

  • 72-Mbit QDR II SRAM architecture
  • Separate read/write data ports
  • Concurrent read and write transactions
  • Two-word burst on all accesses
  • DDR I/O, 350 MHz (700 MHz data)
  • 1.5-cycle read latency (DOFF=HIGH)
  • 1-cycle read latency (DOFF=LOW)
  • Input clocks K/K and output C/C
  • Echo clocks CQ/CQ for data capture
  • Core VDD 1.7-1.9 V (nom 1.8 V)
  • VDDQ 1.4 V to VDD, VREF range
  • JTAG IEEE 1149.1 boundary scan

产品优势

  • High bandwidth for fast networking
  • No bus turnaround delays
  • Parallel R/W boosts throughput
  • Two-word bursts cut command load
  • DDR at 700 MHz speeds transfers
  • Low-latency reads for tight timing
  • DOFF selects latency vs pipeline
  • Separate clocks ease timing closure
  • Echo clocks simplify PCB capture
  • 1.8 V core helps reduce power
  • HSTL levels fit high-speed links
  • JTAG speeds board test and debug

应用

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