CY7C1543KV18-400BZI
现货，推荐

CY7C1543KV18-400BZI

数据手册
封装

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CY7C1543KV18-400BZI
CY7C1543KV18-400BZI
数据手册


商品详情

  • Frequency
    400 MHz
  • 密度
    72 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Pb
  • 接口
    Parallel
  • 系列
    QDR-II+
  • 组织(X x Y)
    4M x 18
  • 质量等级
    Industrial

推荐的
OPN
CY7C1543KV18-400BZI
产品状态 active and preferred
英飞凌封装名称
P-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 136
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 No
无卤素 Yes
符合RoHS标准 No
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
P-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 136
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C1543KV18-400BZI is a 72-Mbit QDR II+ synchronous pipelined SRAM (4M × 18) with separate read and write ports for concurrent transactions and no data bus turn-around. It supports 2.0-cycle read latency and DDR I/O (900 MHz data) at up to 400 MHz clock. It runs from 1.8 V VDD (1.7–1.9 V) with 1.4 V to VDD VDDQ, and is offered in a 165-ball FBGA for industrial -40 to +85°C operation.

特性

  • Separate read and write ports
  • DDR on read and write ports
  • 450 MHz clock operation
  • 900 MHz data transfer at 450 MHz
  • Four-word burst per access
  • 2-cycle read latency (DOFF HIGH)
  • 1-cycle read latency (DOFF LOW)
  • Input clocks K and K (rising edge)
  • Echo clocks CQ and CQ for capture
  • QVLD data-valid output indicator
  • ZQ programmable output impedance
  • IEEE 1149.1 JTAG boundary scan

产品优势

  • No bus turn-around or contention
  • Maximizes bandwidth for fast links
  • Lower address rate eases PCB routing
  • Selectable latency aids timing closure
  • Echo clocks simplify data capture
  • QVLD reduces read timing uncertainty
  • Impedance match improves signal SI
  • PLL keeps data placement accurate
  • Depth expansion without added waits
  • Byte writes avoid read-modify-write
  • VDDQ 1.4 V to VDD eases interfacing
  • JTAG speeds board bring-up and test

应用

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