CY7C1618KV18-333BZXC
现货，推荐
符合RoHS标准
无铅

CY7C1618KV18-333BZXC

数据手册
封装

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CY7C1618KV18-333BZXC
CY7C1618KV18-333BZXC
数据手册


商品详情

  • ECC
    N
  • Frequency
    333 MHz
  • 密度
    144 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    0 °C 至 70 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 数据宽度
    x 18
  • 架构
    DDR-II CIO
  • 片上端接
    N
  • 系列
    DDR-II CIO
  • 组织(X x Y)
    8Mb x 18
  • 脉冲长度 (Words)
    2
  • 读取延迟(周期)
    1.5
  • 质量等级
    Commercial
  • 银行切换
    N

推荐的
OPN
CY7C1618KV18-333BZXC
产品状态 active and preferred
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 525
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 525
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C1618KV18-333BZXC is a 144-Mbit (8M × 18) synchronous pipelined SRAM with a DDR II interface. It supports 333 MHz clocks with double data rate transfers (666 MHz data rate) and a two-word burst counter that uses A0 for burst sequencing. It provides separate K/K and C/C clocks plus CQ/CQ echo clocks for data capture, operates at 1.7 V to 1.9 V VDD with 1.4 V to VDD VDDQ, and comes in a 165-ball Pb-free FBGA.

特性

  • 144-Mbit DDR II synchronous SRAM
  • 333 MHz clock; 666 MHz data rate
  • Two-word burst with 1-bit counter
  • 1.5-cycle latency with DOFF high
  • 1-cycle latency DDR I mode (DOFF)
  • Dual input clocks K/K for DDR
  • Output clocks C/C or single-clock
  • Echo clocks CQ/CQ for data capture
  • Programmable impedance via ZQ pin
  • RQ 175–350 Ω for ±15% match
  • PLL runs 120 MHz to fMAX
  • JTAG IEEE 1149.1 boundary scan

产品优势

  • High bandwidth for fast access
  • More throughput at lower fCLK
  • Less address toggling reduces EMI
  • Latency options ease integration
  • K/K clocks simplify DDR timing
  • C/C clocks help reduce skew
  • CQ/CQ eases high-speed capture
  • ZQ trim improves signal integrity
  • Trace match cuts reflections
  • PLL improves data placement timing
  • JTAG speeds board test and debug
  • Depth expand without added waits

应用

文档

设计资源

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