CY7C2642KV18-333BZXC
现货，推荐
符合RoHS标准
无铅

CY7C2642KV18-333BZXC

数据手册
封装

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CY7C2642KV18-333BZXC
CY7C2642KV18-333BZXC
数据手册


商品详情

  • ECC
    N
  • Frequency
    333 MHz
  • 密度
    144 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    0 °C 至 70 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 数据宽度
    x 18
  • 架构
    QDR-II+, ODT
  • 片上端接
    Y
  • 系列
    QDR-II+, ODT
  • 组织(X x Y)
    8Mb x 18
  • 脉冲长度 (Words)
    2
  • 读取延迟(周期)
    2
  • 质量等级
    Commercial
  • 银行切换
    N

推荐的
OPN
CY7C2642KV18-333BZXC
产品状态 active and preferred
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 210
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 210
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C2642KV18-333BZXC is a 144-Mbit QDR II+ synchronous pipelined SRAM (8 M × 18) with separate read and write ports for concurrent transactions. It supports 333 MHz operation with DDR interfaces on both ports (666 MHz data rate) and 2.0-cycle read latency. Supplies are 1.7–1.9 V VDD and 1.4 V to VDD I/O (VDDQ). It comes in a 165-ball Pb-free FBGA package for commercial temperature range.

特性

  • QDR II+ two-word burst arch
  • 2.0-cycle read latency (DOFF Hi)
  • 333 MHz clock; 666 MHz DDR data
  • Independent read and write ports
  • Concurrent read/write transactions
  • ODT on D, BWS, and K/K inputs
  • Programmable output impedance (RQ)
  • Echo clocks (CQ/CQ) for capture
  • QVLD data-valid output indicator
  • PLL locks at frequencies to 120 MHz
  • Core VDD 1.8 V ±0.1 V
  • VDDQ 1.4 V to VDD; VREF 0.68 V

产品优势

  • No bus turnaround, higher throughput
  • Burst lowers address bus frequency
  • 666 MHz DDR enables high bandwidth
  • Separate ports avoid R/W contention
  • Concurrency boosts system efficiency
  • ODT cuts external resistor BOM
  • Programmable RQ improves signal
  • Echo clocks ease timing closure
  • QVLD simplifies valid-data capture
  • PLL improves data placement margin
  • 1.8 V core reduces power per bit
  • Lower VDDQ can cut I/O power

应用

文档

设计资源

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