CY7C1372KVE33-167AXI
现货,推荐
符合RoHS标准
无铅

CY7C1372KVE33-167AXI

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1372KVE33-167AXI
CY7C1372KVE33-167AXI


商品详情

  • ECC
    Y
  • Frequency
    167 MHz
  • 密度
    18 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 范围
    3.135 V 至 3.6 V
  • 引线球表面
    Pure Sn
  • 接口
    Parallel
  • 数据宽度
    x 18
  • 架构
    NoBL, Pipeline
  • 片上端接
    N
  • 目前计划的可用性至少到
    2031
  • 系列
    Synchronous SRAM with ECC
  • 组织(X x Y)
    1Mb x 18
  • 脉冲长度 (Words)
    4
  • 读取延迟(周期)
    2
  • 质量等级
    Industrial
  • 银行切换
    N

OPN
CY7C1372KVE33-167AXI
产品状态 active and preferred
英飞凌封装名称
封装名 TQFP-100 (51-85050)
封装尺寸 360
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
预估长期供货截止日期 2031
产品发布日期 03/2022
封装产地
TW
晶圆产地
TW

产品状态
Active
英飞凌封装名称
封装名 TQFP-100 (51-85050)
封装尺寸 360
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
预估长期供货截止日期 2031
产品发布日期 03/2022
封装产地
TW
晶圆产地
TW
CY7C1372KVE33-167AXI is an 18-Mbit (1M × 18) synchronous pipelined burst SRAM with No Bus Latency (NoBL) architecture and on-chip ECC. It operates from 3.135 V to 3.6 V core supply with 2.5 V or 3.3 V I/O (VDDQ). The device supports 167 MHz zero-wait-state bus operation, fully registered inputs/outputs, byte write, linear or interleaved burst, CEN clock suspend, and ZZ sleep mode.

特性

  • 250 MHz synchronous burst SRAM
  • Zero wait-state read/write switching
  • No Bus Latency (NoBL) architecture
  • Fully registered I/O for pipelining
  • Clock-to-output tCO 2.5 ns max
  • Burst counter, up to 4 transfers
  • Linear or interleaved burst order
  • Byte write with BWx signals
  • Self-timed synchronous write logic
  • 3 chip enables + async OE tri-state
  • ZZ sleep mode, data retained
  • IEEE 1149.1 JTAG boundary scan

产品优势

  • High throughput at 250 MHz bus
  • Fast turnarounds, no wait states
  • Sustains back-to-back R/W cycles
  • Predictable timing for high-speed
  • 2.5 ns tCO reduces read latency
  • 4-beat bursts reduce addr toggles
  • Burst modes match bus protocols
  • Byte writes cut RMW overhead
  • No write timing tuning needed
  • Easy bank expansion, avoids fights
  • Sleep cuts standby, keeps data
  • JTAG simplifies board test/debug

应用

文档

设计资源

开发者社区