xSPI生态系统支持

全面的芯片组兼容性、丰富的开发平台生态系统以及控制器和验证 IP 供应商

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About

x8 serial bus interface

Expanded Serial Peripheral Interface (xSPI) for non-volatile memory devices is a high throughput, low pin count interface which offers some backwards compatibility with legacy SPI devices. JESD251 (the controlling JEDEC specification) includes two types of interface: Profile 1.0 for Octal, and Profile 2.0 for HYPERBUS™. Standardization of the interface enables broad industry support, and Infineon is a key advocate for continued development and adoption of xSPI-compatible products.

xSPI (Profile 2.0) is the successor to HYPERBUS™

HYPERBUS™ was originally developed by Cypress Semiconductor / Spansion in 2014. It is a high performance / low pin-count serial memory interface, broadly supported by chipset vendors and other ecosystem players. In 2018, HYPERBUS™ was further codified by JEDEC in JESD251, the xSPI standard. Original HYPERBUS™ continues to be supported and enhanced, with considerations for doubling bus width to 16 bits. However, most products will gravitate towards xSPI Octal and xSPI HYPERBUS™ interfaces going forward.

Infineon memory with other interfaces

Infineon memory is available across a broad range of interfaces, including parallel, quad SPI, Octal (xSPI Profile 1.0), HYPERBUS™ (original), and HYPERBUS™ (xSPI Profile 2.0). We work with chipset vendors worldwide to test, integrate, and validate our memories to make it easy to integrate our products into your design. To see a complete list of partners and chipset pairings, visit our memory chipset partner page.

View all chipset partners

x8 serial bus interface

Expanded Serial Peripheral Interface (xSPI) for non-volatile memory devices is a high throughput, low pin count interface which offers some backwards compatibility with legacy SPI devices. JESD251 (the controlling JEDEC specification) includes two types of interface: Profile 1.0 for Octal, and Profile 2.0 for HYPERBUS™. Standardization of the interface enables broad industry support, and Infineon is a key advocate for continued development and adoption of xSPI-compatible products.

xSPI (Profile 2.0) is the successor to HYPERBUS™

HYPERBUS™ was originally developed by Cypress Semiconductor / Spansion in 2014. It is a high performance / low pin-count serial memory interface, broadly supported by chipset vendors and other ecosystem players. In 2018, HYPERBUS™ was further codified by JEDEC in JESD251, the xSPI standard. Original HYPERBUS™ continues to be supported and enhanced, with considerations for doubling bus width to 16 bits. However, most products will gravitate towards xSPI Octal and xSPI HYPERBUS™ interfaces going forward.

Infineon memory with other interfaces

Infineon memory is available across a broad range of interfaces, including parallel, quad SPI, Octal (xSPI Profile 1.0), HYPERBUS™ (original), and HYPERBUS™ (xSPI Profile 2.0). We work with chipset vendors worldwide to test, integrate, and validate our memories to make it easy to integrate our products into your design. To see a complete list of partners and chipset pairings, visit our memory chipset partner page.

View all chipset partners