CY7C1514KV18-300BZXI
现货，推荐
符合RoHS标准
无铅

CY7C1514KV18-300BZXI

数据手册
封装

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CY7C1514KV18-300BZXI
CY7C1514KV18-300BZXI
数据手册


商品详情

  • ECC
    N
  • Frequency
    300 MHz
  • 密度
    72 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 数据宽度
    x 36
  • 架构
    QDR-II
  • 片上端接
    N
  • 系列
    QDR-II
  • 组织(X x Y)
    2Mb x 36
  • 脉冲长度 (Words)
    2
  • 读取延迟(周期)
    1.5
  • 质量等级
    Industrial
  • 银行切换
    N

推荐的
OPN
CY7C1514KV18-300BZXI
产品状态 active and preferred
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 1360
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 1360
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C1514KV18-300BZXI is a 1.8 V QDR II synchronous pipelined SRAM organized as 2M × 36 (72 Mbit). It uses separate read and write ports with DDR interfaces and a two-word burst, eliminating bus turnaround and enabling concurrent transactions. Rated for 300 MHz clock operation, it supports single clock mode, echo clocks (CQ/CQ), and 1.5-cycle read latency with DOFF HIGH (1-cycle QDR I mode with DOFF LOW).

特性

  • 72-Mbit QDR II SRAM architecture
  • Separate read/write data ports
  • Concurrent read and write transactions
  • Two-word burst on all accesses
  • DDR I/O, 350 MHz (700 MHz data)
  • 1.5-cycle read latency (DOFF=HIGH)
  • 1-cycle read latency (DOFF=LOW)
  • Input clocks K/K and output C/C
  • Echo clocks CQ/CQ for data capture
  • Core VDD 1.7-1.9 V (nom 1.8 V)
  • VDDQ 1.4 V to VDD, VREF range
  • JTAG IEEE 1149.1 boundary scan

产品优势

  • High bandwidth for fast networking
  • No bus turnaround delays
  • Parallel R/W boosts throughput
  • Two-word bursts cut command load
  • DDR at 700 MHz speeds transfers
  • Low-latency reads for tight timing
  • DOFF selects latency vs pipeline
  • Separate clocks ease timing closure
  • Echo clocks simplify PCB capture
  • 1.8 V core helps reduce power
  • HSTL levels fit high-speed links
  • JTAG speeds board test and debug

应用

文档

设计资源

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