CY7C1565KV18-400BZXI
现货，推荐
符合RoHS标准
无铅

CY7C1565KV18-400BZXI

数据手册
封装

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CY7C1565KV18-400BZXI
CY7C1565KV18-400BZXI
数据手册


商品详情

  • Frequency
    400 MHz
  • 密度
    72 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 系列
    QDR-II+
  • 组织(X x Y)
    2M x 36
  • 质量等级
    Industrial

推荐的
OPN
CY7C1565KV18-400BZXI
产品状态 active and preferred
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 272
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 272
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C1565KV18-400BZXI is a 72-Mbit (2M × 36) QDR II+ synchronous pipelined SRAM with independent read and write DDR ports for concurrent transactions. It supports four-word burst operation and 2.5-cycle read latency (1-cycle with DOFF low), with maximum clock frequency 400 MHz. Runs from 1.7–1.9 V core and 1.4 V to VDDQ I/O, with echo clocks (CQ/CQ) and QVLD data-valid output, in 165-ball FBGA Pb-free industrial grade.

特性

  • QDR II+ four-word burst
  • Separate read/write data ports
  • DDR I/O on read and write ports
  • 2.5-cycle read latency (DOFF=H)
  • 1-cycle read latency (DOFF=L)
  • 550 MHz maximum clock
  • Data valid 0.45 ns from clock edge
  • Echo clocks CQ/CQ for capture
  • QVLD asserts 0.5 cycle before data
  • Programmable output impedance (RQ)
  • On-chip PLL operates down to 120 MHz
  • IEEE 1149.1 JTAG boundary scan

产品优势

  • No bus turnaround, less contention
  • DDR at 550 MHz boosts bandwidth
  • 4-word burst cuts addr bus rate
  • Selectable latency eases timing
  • 1-cycle mode reduces read delay
  • 0.45 ns valid supports tight timing
  • CQ/CQ simplifies data capture
  • QVLD eases strobe and timing align
  • RQ matching improves signal integrity
  • PLL improves data placement accuracy
  • Depth expansion without wait states
  • JTAG speeds board test and debug

应用

文档

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