CY7C1612KV18-250BZXC
现货，推荐
符合RoHS标准
无铅

CY7C1612KV18-250BZXC

数据手册
封装

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CY7C1612KV18-250BZXC
CY7C1612KV18-250BZXC
数据手册


商品详情

  • ECC
    N
  • Frequency
    250 MHz
  • 密度
    144 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    0 °C 至 70 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 数据宽度
    x 18
  • 架构
    QDR-II
  • 片上端接
    N
  • 系列
    QDR-II
  • 组织(X x Y)
    8Mb x 18
  • 脉冲长度 (Words)
    2
  • 读取延迟(周期)
    1.5
  • 质量等级
    Commercial
  • 银行切换
    N

推荐的
OPN
CY7C1612KV18-250BZXC
产品状态 active and preferred
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 525
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 525
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C1612KV18-250BZXC is a 144-Mbit QDR II synchronous pipelined SRAM in an 8M × 18 organization. It uses separate read and write ports with DDR interfaces and a two-word burst, eliminating data bus turnarounds and supporting concurrent transactions. The 250 MHz speed grade operates from 1.8 V core (±0.1 V) with 1.4 V to VDDQ I/O supply, and supports 1.5-cycle read latency (DOFF high).

特性

  • Dual read/write data ports
  • 360 MHz clock operation
  • DDR I/O, 720 MHz data transfer
  • Two-word burst on all accesses
  • Two input clocks K and K
  • Separate output clocks C and C
  • Echo clocks CQ and CQ
  • 1.5-cycle read latency (DOFF=1)
  • 1-cycle read latency (DOFF=0)
  • 1.8 V VDD supply
  • VDDQ = 1.4 V to VDD
  • IEEE 1149.1-2001 JTAG TAP

产品优势

  • No bus turnaround, more bandwidth
  • Concurrent reads and writes
  • Fast throughput at 360 MHz
  • Echo clocks ease data capture
  • C/C clocks reduce skew issues
  • Flexible latency eases timing
  • PLL improves data placement
  • JTAG simplifies board test
  • Port selects enable depth scaling
  • VDDQ range eases I/O matching
  • Defined power-up prevents faults
  • Low SER improves data integrity

应用

文档

设计资源

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