CY7C25652KV18-400BZXI
现货，推荐
符合RoHS标准
无铅

CY7C25652KV18-400BZXI

数据手册
封装

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CY7C25652KV18-400BZXI
CY7C25652KV18-400BZXI
数据手册


商品详情

  • Frequency
    400 MHz
  • 密度
    72 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 系列
    QDR-II+, ODT
  • 组织(X x Y)
    2Mb x 36
  • 质量等级
    Industrial

推荐的
OPN
CY7C25652KV18-400BZXI
产品状态 active and preferred
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 136
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 136
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C25652KV18-400BZXI is a 72-Mbit QDR II+ synchronous pipelined SRAM in a 2M × 36 organization with separate read and write ports for concurrent transactions. It supports a four-word burst, 2.5-cycle read latency, and DDR interfaces on both ports (data transfer on every clock edge). It runs from 1.7–1.9 V VDD with 1.4 V to VDD VDDQ, in a 165-ball FBGA, industrial -40 to +85°C range.

特性

  • 550 MHz clock (1100 MHz DDR data)
  • Separate read and write data ports
  • Concurrent read/write transactions
  • Four-word burst architecture
  • 2.5-cycle read latency (DOFF HIGH)
  • 1-cycle read latency mode (DOFF LOW)
  • Two input clocks (K and K)
  • Echo clocks CQ/CQ for data capture
  • QVLD pin indicates valid read data
  • On-die termination for D/BWS/K
  • PLL runs down to 120 MHz
  • Core VDD 1.7 V to 1.9 V

产品优势

  • High bandwidth for fast DSP/ASIC
  • No bus turn-around delays
  • Read and write run in parallel
  • Lower address bus frequency
  • Deterministic 2.5-cycle reads
  • 1-cycle reads for low latency
  • Simpler DDR timing with K/K
  • Easier high-speed data capture
  • QVLD reduces timing margin effort
  • ODT cuts external termination BOM
  • PLL improves data placement margin
  • 1.8 V core reduces power vs 2.5 V

应用

文档

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