CY7C2663KV18-450BZI
现货，推荐

CY7C2663KV18-450BZI

数据手册
封装

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C2663KV18-450BZI
CY7C2663KV18-450BZI
数据手册


商品详情

  • ECC
    N
  • Frequency
    450 MHz
  • 密度
    144 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Pb
  • 接口
    Parallel
  • 数据宽度
    x 18
  • 架构
    QDR-II+, ODT
  • 片上端接
    Y
  • 系列
    QDR-II+, ODT
  • 组织(X x Y)
    8Mb x 18
  • 脉冲长度 (Words)
    4
  • 读取延迟(周期)
    2.5
  • 质量等级
    Industrial
  • 银行切换
    N

推荐的
OPN
CY7C2663KV18-450BZI
产品状态 active and preferred
英飞凌封装名称
P-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 105
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 No
无卤素 Yes
符合RoHS标准 No
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
P-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 105
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C2663KV18-450BZI is a 144-Mbit QDR II+ synchronous pipelined SRAM in an 8M × 18 organization with separate read and write ports for concurrent transactions. It supports 2.5-cycle read latency, four-word burst, and DDR I/O (data transfer at 1100 MHz) with a 450 MHz max clock. Operates at VDD 1.7–1.9 V and VDDQ 1.4 V to VDD, with ODT and echo clocks (CQ/CQ) in a 165-ball FBGA, industrial -40 to 85°C.

特性

  • QDR II+ SRAM, 4-word burst
  • 550 MHz clock, 1100 MHz DDR data
  • Separate read/write data ports
  • Supports concurrent transactions
  • 2.5-cycle read latency (DOFF=1)
  • 1-cycle read latency mode (DOFF=0)
  • On-die termination for D/BWS/K
  • Echo clocks (CQ/CQ) for capture
  • QVLD pin indicates valid output data
  • PLL locks with 20 µs stable clock
  • PLL operates down to 120 MHz
  • VDD 1.7–1.9 V; VDDQ 1.4 V–VDD

产品优势

  • High bandwidth with fewer addresses
  • Faster transfers at 1100 MHz DDR
  • No bus turnarounds, lower latency
  • Read+write same time boosts throughput
  • Predictable 2.5-cycle read timing
  • 1-cycle reads cut access delay
  • ODT reduces external termination BOM
  • CQ/CQ eases timing at high speed
  • QVLD simplifies receive data capture
  • PLL stabilizes data placement
  • Runs PLL even at 120 MHz clocks
  • Works with 1.4 V or 1.5 V I/O

应用

文档

设计资源

合作伙伴解决方案

开发者社区