CY7C1520KV18-250BZCT
现货，推荐

CY7C1520KV18-250BZCT

数据手册
封装

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CY7C1520KV18-250BZCT
CY7C1520KV18-250BZCT
数据手册


商品详情

  • Frequency
    250 MHz
  • 密度
    72 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    0 °C 至 70 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Pb
  • 接口
    Parallel
  • 系列
    DDR-II CIO
  • 组织(X x Y)
    2M x 36
  • 质量等级
    Commercial

推荐的
OPN
CY7C1520KV18-250BZCT
产品状态 active and preferred
英飞凌封装名称
P-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 1000
封装类型 TAPE & REEL
湿度 3
防潮封装 DRY
无铅 No
无卤素 Yes
符合RoHS标准 No
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
P-BGA-165
封装名 FBGA-165 (51-85180)
封装尺寸 1000
封装类型 TAPE & REEL
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C1520KV18-250BZCT is a 72-Mbit (2M × 36) synchronous pipelined DDR-II SRAM with two-word burst operation. It supports up to 250 MHz clocking (DDR transfers at 500 MHz) and selectable read latency: 1.5 cycles with PLL enabled (DOFF HIGH) or 1 cycle DDR-I mode with DOFF LOW. HSTL I/Os support 1.5 V/1.8 V VDDQ, with echo clocks (CQ/CQ), ZQ impedance match, and JTAG 1149.1 test access.

特性

  • 72-Mbit DDR-II sync SRAM
  • 333 MHz clock, 666 MHz data xfer
  • Two-word burst, 1-bit counter
  • 1.5-cycle read latency (DOFF HI)
  • 1-cycle read latency (DOFF LO)
  • Dual input clocks K/K
  • Dual output clocks C/C
  • Echo clocks CQ/CQ
  • Byte write via BWS signals
  • ZQ sets output impedance
  • PLL runs 120 MHz to fMAX
  • IEEE 1149.1 JTAG boundary scan

产品优势

  • High bandwidth at 333 MHz clocks
  • Cuts addr bus rate with 2-word burst
  • Latency option fits DDR-I/DDR-II
  • Improves DDR timing with K/K clocks
  • Reduces skew using C/C clocks
  • Simplifies capture with CQ/CQ clocks
  • Byte writes avoid read-modify-write
  • Impedance control improves SI
  • PLL stabilizes high-speed timing
  • Depth expansion without wait states
  • Pipeline starts every K rising edge
  • Eases board test with JTAG scan

应用

文档

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