CY7C2644KV18-300BZXI
现货，推荐
符合RoHS标准
无铅

CY7C2644KV18-300BZXI

数据手册
封装

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CY7C2644KV18-300BZXI
CY7C2644KV18-300BZXI
数据手册


商品详情

  • ECC
    N
  • Frequency
    300 MHz
  • 密度
    144 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 数据宽度
    x 36
  • 架构
    QDR-II+, ODT
  • 片上端接
    Y
  • 系列
    QDR-II+, ODT
  • 组织(X x Y)
    4Mb x 36
  • 脉冲长度 (Words)
    2
  • 读取延迟(周期)
    2.5
  • 质量等级
    Industrial
  • 银行切换
    N

推荐的
OPN
CY7C2644KV18-300BZXI
产品状态 active and preferred
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 105
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 105
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C2644KV18-300BZXI is a 144-Mbit QDR II+ synchronous pipelined SRAM with separate read and write ports and a two-word burst architecture. It transfers data on both edges of K/K clocks (DDR, 500 MHz at 250 MHz) with 2.0-cycle read latency, echo clocks (CQ/CQ), QVLD, and on-die termination for D, BWS, and K/K. It runs from 1.8 V core (VDD 1.7–1.9 V) and 1.4 V to VDD I/O (VDDQ), in a 165-ball CCGA.

特性

  • QDR II+ dual-port read/write
  • Two-word burst per address
  • DDR I/O at 250 MHz (500 MHz)
  • Separate D and Q buses (no turn)
  • 2-cycle read latency (DOFF high)
  • QDR I mode, 1-cycle read latency
  • ODT for D/BWS and K/K inputs
  • Echo clocks CQ/CQ for capture
  • QVLD indicates valid output data
  • PLL runs 120 MHz to 250 MHz
  • ZQ resistor sets driver impedance
  • VDD 1.7–1.9 V; VDDQ 1.4 V–VDD

产品优势

  • Full-duplex access boosts bandwidth
  • Burst cuts address bus frequency
  • 250 MHz interface meets fast links
  • No turnaround prevents contention
  • 2-cycle latency eases timing closure
  • QDR I mode supports legacy timing
  • ODT reduces external resistor BOM
  • CQ/CQ simplify high-speed capture
  • QVLD improves read data confidence
  • PLL tightens output timing margins
  • Impedance match reduces ringing
  • VDD/VDDQ range eases power design

应用

文档

设计资源

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