CY7C1041GN-10ZSXI
现货,推荐
符合RoHS标准
无铅

CY7C1041GN-10ZSXI

Content could not be loaded

Unfortunately, we were unable to load the content for this section. You may want to refresh the page or try again later.

CY7C1041GN-10ZSXI
CY7C1041GN-10ZSXI


商品详情

  • 密度
    4 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    -40 °C 至 85 °C
  • 工作电压 (VCCQ) 范围
    4.5 V 至 5.5 V
  • 工作电压 范围
    4.5 V 至 5.5 V
  • 引线球表面
    Ni/Pd/Au
  • 接口
    Parallel
  • 目前计划的可用性至少到
    2033
  • 系列
    FAST SRAM
  • 组织(X x Y)
    256K x 16
  • 质量等级
    Industrial
  • 速度
    10 ns

OPN
CY7C1041GN-10ZSXI
产品状态 active and preferred
英飞凌封装名称
封装名 TSOP-II-44 (51-85087)
封装尺寸 675
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
预估长期供货截止日期 2033
产品发布日期 03/2022
封装产地
PH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
封装名 TSOP-II-44 (51-85087)
封装尺寸 675
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
预估长期供货截止日期 2033
产品发布日期 03/2022
封装产地
PH
晶圆产地
TW
CY7C1041GN-10ZSXI is a 4-Mbit fast asynchronous CMOS SRAM organized as 256K × 16. It supports 10 ns address access and byte writes/reads via BLE and BHE, with CE/WE-controlled writes and CE/OE-controlled reads. The industrial-grade device operates from 4.5 V to 5.5 V over -40°C to +85°C, uses TTL-compatible I/Os, and is offered in a Pb-free 44-pin TSOP II package. It specifies ICC up to 45 mA at fmax and ISB2 standby up to 8 mA.

特性

  • 4-Mbit SRAM, 256K × 16
  • tAA access time 10 ns / 15 ns
  • 18-bit address bus A0 to A17
  • 16-bit I/O bus I/O0 to I/O15
  • Byte write enables BHE and BLE
  • CE and OE control read, HI-Z
  • Data retention down to 1.0 V
  • VDR = 1 V for data retention
  • tRC read cycle 10 ns / 15 ns
  • tDOE OE to data 4.5 ns / 8 ns
  • Standby current ISB2 6 mA typ
  • Input/output leakage ±1 µA

产品优势

  • Fast 10 ns access cuts latency
  • 16-bit bus boosts throughput
  • Byte writes reduce write traffic
  • HI-Z outputs ease bus sharing
  • 1.0 V retention preserves data
  • Wide VCC options fit many rails
  • Low standby current saves power
  • Low leakage supports low power
  • Simple CE/OE/WE control logic
  • Quick OE access speeds reads
  • Predictable 10/15 ns cycles
  • Stable levels ease interfacing
文档

设计资源

开发者社区