CY7C4042KV13-933FCXC
现货,推荐
符合RoHS标准
无铅

CY7C4042KV13-933FCXC

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CY7C4042KV13-933FCXC
CY7C4042KV13-933FCXC


商品详情

  • ECC
    Y
  • Frequency
    933 MHz
  • 密度
    72 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    0 °C 至 70 °C
  • 工作电压 范围
    1.26 V 至 1.34 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 数据宽度
    x 36
  • 架构
    QDR-IV
  • 片上端接
    Y
  • 目前计划的可用性至少到
    2031
  • 系列
    QDR-IV
  • 组织(X x Y)
    2Mb x 36
  • 脉冲长度 (Words)
    2
  • 读取延迟(周期)
    8
  • 质量等级
    Commercial
  • 银行切换
    Y

OPN
CY7C4042KV13-933FCXC
产品状态 active and preferred
英飞凌封装名称
封装名 FCBGA-361 (001-70319)
封装尺寸 600
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
预估长期供货截止日期 2031
产品发布日期 03/2022
封装产地
TW
晶圆产地
TW

产品状态
Active
英飞凌封装名称
封装名 FCBGA-361 (001-70319)
封装尺寸 600
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
预估长期供货截止日期 2031
产品发布日期 03/2022
封装产地
TW
晶圆产地
TW
CY7C4042KV13-933FCXC is a 72-Mbit QDR-IV XP SRAM in a 2M × 36 organization with dual independent bidirectional DDR data ports and a single DDR address bus. The 933 speed grade supports up to 933 MHz (1866 MT/s) with two-word bursts, 8-bank architecture (one access per bank per cycle), and fixed read latency 8 cycles and write latency 5 cycles. It uses 1.3 V VDD and is offered in a 361-ball Pb-free FCBGA.

特性

  • 72-Mbit synchronous SRAM
  • 2132 MT/s random transaction rate
  • 1066 MHz max operating frequency
  • Read latency: 8 clock cycles
  • Write latency: 5 clock cycles
  • Dual bidirectional DDR data ports
  • DDR address, SDR control signaling
  • 8 internal banks, 1 access/bank
  • Two-word burst on all accesses
  • On-die termination (ODT)
  • Address and data bus inversion
  • On-chip ECC + address parity

产品优势

  • Handles high-bandwidth workloads
  • Enables 1066 MHz high-speed access
  • Predictable 8-cycle read timing
  • Short write latency reduces stalls
  • Full-duplex read/write bandwidth
  • Shared addr bus simplifies routing
  • Banking sustains parallel accesses
  • Burst-2 improves bus efficiency
  • ODT improves signal integrity
  • Bus inversion cuts SSN and EMI
  • ECC improves data reliability
  • Parity helps catch addr faults

应用

文档

设计资源

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