CY7C1663KV18-550BZXC
现货，推荐
符合RoHS标准
无铅

CY7C1663KV18-550BZXC

数据手册
封装

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CY7C1663KV18-550BZXC
CY7C1663KV18-550BZXC
数据手册


商品详情

  • ECC
    N
  • Frequency
    550 MHz
  • 密度
    144 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    0 °C 至 70 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 数据宽度
    x 18
  • 架构
    QDR-II+
  • 片上端接
    N
  • 系列
    QDR-II+
  • 组织(X x Y)
    8Mb x 18
  • 脉冲长度 (Words)
    4
  • 读取延迟(周期)
    2.5
  • 质量等级
    Commercial
  • 银行切换
    N

推荐的
OPN
CY7C1663KV18-550BZXC
产品状态 active and preferred
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 210
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
PG-BGA-165
封装名 FBGA-165 (51-85195)
封装尺寸 210
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C1663KV18-550BZXC is a 144-Mbit (8 M × 18) QDR II+ synchronous pipelined SRAM with separate read and write ports and a four-word burst architecture. It supports a 550 MHz clock with DDR transfers (1100 MHz data rate) and 2.5-cycle read latency. The device operates from 1.7–1.9 V VDD with 1.4 V–VDD VDDQ and is offered in a 165-ball Pb-free FBGA package for high-bandwidth networking, DSP, and packet buffering.

特性

  • 550 MHz clock, DDR at 1100 MHz
  • Four-word burst (sequential)
  • Separate read and write data ports
  • Concurrent read/write transactions
  • Read latency 2.5 cycles (DOFF=H)
  • QDR I mode, 1-cycle latency (DOFF=L)
  • Two input clocks K/K for DDR timing
  • Echo clocks CQ/CQ for data capture
  • QVLD data-valid, 0.5-cycle early
  • Programmable output impedance via RQ
  • On-chip PLL locks after 20 µs
  • IEEE 1149.1 JTAG boundary scan

产品优势

  • High bandwidth for fast packets
  • Lower addr bus frequency
  • No I/O bus turnaround delays
  • Read/write same time, less stalls
  • Predictable 2.5-cycle reads
  • Switch to 1-cycle for low latency
  • Easier timing closure at high speed
  • Simpler data capture, less skew
  • Clean valid window for receivers
  • Better signal integrity, fewer SI fixes
  • Accurate data placement after power-up
  • Faster board debug and test access

应用

文档

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