CY7C25682KV18-550BZXC
现货,推荐
符合RoHS标准
无铅

CY7C25682KV18-550BZXC

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CY7C25682KV18-550BZXC
CY7C25682KV18-550BZXC


商品详情

  • ECC
    N
  • Frequency
    550 MHz
  • 密度
    72 MBit
  • 峰值回流温度
    260 °C
  • 工作温度 范围
    0 °C 至 70 °C
  • 工作电压 范围
    1.7 V 至 1.9 V
  • 引线球表面
    Sn/Ag/Cu
  • 接口
    Parallel
  • 数据宽度
    x 18
  • 架构
    DDR-II+ CIO, ODT
  • 片上端接
    Y
  • 系列
    DDR-II+ CIO, ODT
  • 组织(X x Y)
    4Mb x 18
  • 脉冲长度 (Words)
    2
  • 读取延迟(周期)
    2.5
  • 质量等级
    Commercial
  • 银行切换
    N

OPN
CY7C25682KV18-550BZXC
产品状态 active and preferred
英飞凌封装名称
封装名 FBGA-165 (51-85180)
封装尺寸 680
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅 Yes
无卤素 Yes
符合RoHS标准 Yes
封装产地
TH
晶圆产地
TW

产品状态
Active
英飞凌封装名称
封装名 FBGA-165 (51-85180)
封装尺寸 680
封装类型 TRAY
湿度 3
防潮封装 DRY
无铅
无卤素
符合 RoHS 标准
封装产地
TH
晶圆产地
TW
CY7C25682KV18-550BZXC is a 72-Mbit DDR II+ synchronous pipelined SRAM organized as 4M × 18 with a two-word burst architecture. It runs up to 550 MHz clock (1100 MHz DDR transfer) with 2.5-cycle read latency, using K/K input clocks for DDR timing. It operates from 1.7 V to 1.9 V VDD and 1.4 V to VDD VDDQ, and integrates ODT, CQ/CQ echo clocks, QVLD data-valid, PLL, and IEEE 1149.1 JTAG.

特性

  • 72-Mbit DDR II+ SRAM
  • Two-word burst architecture
  • 550 MHz clock, 1100 MHz DDR data
  • 2.5-cycle read latency (DOFF=HIGH)
  • DDR I mode: 1-cycle latency
  • Dual input clocks K/K
  • Echo clocks CQ/CQ
  • QVLD data-valid indicator
  • ODT on D, BWS, and K/K inputs
  • PLL: 120 MHz to fMAX, 20 us lock
  • Byte write via BWS[x:0]
  • ZQ RQ 175–350 ohm, ±15% match

产品优势

  • 1100 MHz DDR boosts bandwidth
  • Two-word burst cuts addr toggling
  • 2.5-cycle latency fits pipelines
  • DDR I mode eases legacy timing
  • K/K improves DDR timing margin
  • CQ/CQ simplify data capture
  • QVLD reduces strobe tuning effort
  • ODT cuts external resistors and area
  • ZQ matching improves signal integrity
  • PLL improves read data placement
  • Byte writes avoid read-modify-write
  • Power-down lowers standby draw

应用

文档

设计资源

开发者社区